module FPGA_I2C_TOP
(
    input   wire sys_clk,//25M
    input   wire rst_n,

    output  wire scl,
    output  wire sda,

    //*****SIGNAL PASSTHROUGH*****
    //MSI5351 Output
    input   wire fpga_clk3,
    input   wire fpga_clk4,
    input   wire fpga_clk5,

    //FPGA Output
    output  wire pll_clk0,
    output  wire pll_clk1,
    output  wire pll_clk2
);

//*****SIGNAL PASSTHROUGH*****

assign pll_clk0 = fpga_clk3;
assign pll_clk1 = fpga_clk4;
assign pll_clk2 = fpga_clk5;

//*****CONFIG IIC ONE TIME****

wire sys_rst = ~rst_n;

reg [1:0] config_en;

always @ (posedge sys_clk)
    if(sys_rst)
        config_en <= 2'd0;
    else if(config_en[0]||config_en[1])
        config_en <= 2'b10;
    else
        config_en <= 2'b01;
    

i2c_tx_rom_phy # 
(
    .SYS_FREQ(25000000),//XTAL 2
    .IIC_FREQ(100000),
    .WAIT_TIME(0),
    .TRI_STATE(0)
) i2c_phy
(
    .sys_clk(sys_clk),
    .sys_rst(sys_rst),

    .send_config_en(config_en),

    .iic_scl(scl),
    .iic_sda(sda)
);


endmodule